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NXP Semiconductors /MIMXRT1062 /LCDIF /VDCTRL4

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Interpret as VDCTRL4

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DOTCLK_H_VALID_DATA_CNT0 (SYNC_SIGNALS_ON)SYNC_SIGNALS_ON 0DOTCLK_DLY_SEL

Description

LCDIF VSYNC Mode and Dotclk Mode Control Register4

Fields

DOTCLK_H_VALID_DATA_CNT

Total number of DISPLAY CLOCK (pix_clk) cycles on each horizontal line that carry valid data in DOTCLK mode
SYNC_SIGNALS_ON

Set this field to 1 if the LCD controller requires that the VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active at least one frame before the data transfers actually start and remain active at least one frame after the data transfers end
DOTCLK_DLY_SEL

This bitfield selects the amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data